Content addressable memory (CAM) devices are widely used in networking and communications applications. A content addressable memory is one where the contents of the memory are searched by a ‘key’, which relates to the content of each memory location, rather than by an address, as in a conventional memory device.
Conventional CAM devices can include binary CAM devices and ternary CAM (TCAM) devices. Binary CAM devices can provide a match result based on a bit-by-bit comparison between bits of a compare data value and a stored data value. Full TCAM devices can enable a bit-by-bit masking of compare results for each data value. “Pseudo” TCAM (PTCAM) devices can provide masking on a multiple bitwise basis. In particular, matching can be masked on a columnwise basis, with a same bit location within multiple stored data values being masked from a compare operation.
A conventional PTCAM device will now be described with reference to FIG. 12. Conventional PTCAM 1200 includes CAM cells 1202-0 and 1202-1 arranged in a first column, and CAM cells 1202-2 and 1202-3 arranged into a second column. CAM cells (1202-0 and 1202-1) of a first column can receive a first complementary compare data values CD0/BCD0 by way of compare data lines 1204-0 and 1204-1. In the same way, CAM cells (1202-2 and 1202-3) of a second column can receive a second complementary compare data values CD1/BCD1 by way of compare data lines 1204-2 and 1204-3.
In a row direction, CAM cells 1202-0 and 1202-2 can be commonly connected to one match line 1206-0, while CAM cells 1202-1 and 1202-3 can be commonly connected to another match line 1206-1.
In the conventional PTCAM 1200, each column can have a corresponding mask value storage circuit 1208-0 and 1208-1. A mask value storage circuit (1208-0 and 1208-1) can provide a mask value (M0/M1) to CAM cells of the corresponding column.
Referring still to FIG. 12, in the conventional arrangement each CAM cell (1202-0 to 1202-3) can include a storage circuit 1210 and a compare circuit 1212. Each compare circuit 1212 can include six transistors N0 to N5. Transistors N0-N2 and N3-N5 can have source-drain paths arranged in series between a match line (1206-0 or 1206-1) and a low power supply Vss. Transistors N0/N3 can receive complementary compare data values CD0/BCD0 or CD1/BCD1 at their respective gates. Transistors N1/N4 can receive the same mask value M0/M1 for the column at their respective gates. Transistors N2/N5 can receive complementary stored data values V/BV, at their respective gates.
In such a conventional arrangement, a mask value M0/M1 can dictate a match result for the corresponding column. More particularly, if a mask value M0/M1 is low, CAM cells of the corresponding column will not be capable of forming a discharge path for their corresponding match lines, as transistors N1 and N4 can be placed in a high impedance state. However, if a mask value M0/M1 is high, CAM cells of the corresponding column may or may not form a discharge path for their corresponding match lines depending upon a comparison between a stored data value V/BV and applied compare data value CD/BCD.
In this way, in a conventional TCAM, masking of bit compare operations can be performed on a columnwise basis according to a mask value for each column.